CMOS integrated circuits of current technologies require very thorough protection against Electrostatic Discharge (ESD) phenomena. The susceptibility of VLSI CMOS circuits to excessive voltages and currents caused by ESD requires effective protection of all circuit pins. FIG. 1 shows the commonly used protection mechanism, where input protection circuits (PCI) 101a and 101b are used to protect input circuit 111 from undesired ESD voltages received on input pin 101. Similarly, output protection circuits (PCO) 102a and 102b protect output circuit 112 from undesired ESD voltages appearing on output pin 102. Voltage supply protection circuit (PCV) 103 protects the entire circuit from ESD voltages appearing on either one or both of the VSS and VDD supply pins. It has been reported in the article "Internal Chip ESD Phenomena Beyond the Protection Circuit" by Duvvury et. al., IEEE/IRPS, 1988, pages 19-25, that all commonly used protection circuits cause a circuit stress to the "protected" circuit. In other words, circuit protection as it exists today is not very effective.
The common ESD protection practice, as depicted in FIG. 2, is to use grounded gate thick or thin oxide transistors 201a, 201b, 202a, 202b. The drawback of using thin oxide transistors is that the breakdown voltage of the grounded gate transistor approaches the thin oxide breakdown voltage. The breakdown of these transistors in the grounded gate mode is approximately 13-17 volts, depending on dopant concentrations and distributions. The typical oxide breakdown is 15-17 volts for approximately 175 angstrom gate oxide and the grounded gate thin oxide breakdown is 12-14 volts. Thus, the breakdown margin between device breakdown may be inadequate at only several volts.
FIG. 3 is an illustration depicting the proximity of the breakdown region of the grounded gate thin oxide transistor, including source/drain regions 302, 303 lightly doped source/drain extensions 304, 305, thin gate oxide 301, polycrystalline silicon gate electrode 306, and sidewall spacers 307. The channel region is formed between the source/drain extensions 304, 305 within P well 310 in substrate 311. It is influenced by the control voltage applied to polycrystalline silicon gate 306, in this instance VSS, which is also applied to source/drain region 302. The input or output structure to be protected is connected to source/drain region 303. With the breakdown of the thin gate occurring in region 399 so close to thin gate oxide 301, a potentially unreliable device is created. The thin oxide grounded gate configuration is used because this device has a lower breakdown than the thick oxide field transistor; in fact it gives the lowest controlled breakdown voltage of all devices commonly available on the chip today. In fact the thick field transistor, whether operated as grounded gate or high gate, will probably surpass the breakdown voltage of the thin gate oxide and hence is useless for protection. Since the grounded gate thin oxide transistor has a breakdown between 12-14 volts, this limits the thinness of the gate oxide which may be used. The gate oxide breakdown must be greater than the protection device breakdown. Generally for low voltage lap top or portable operation, it is desirable to have maximum drive for a given threshold voltage. One way to accomplish this is by thinning the gate oxide to increase the I.sub.dss of the transistor. If the protection device is limited to 12 volts breakdown, at best this will limit gate oxide to at least 140 angstroms. On the other hand, if 8.0 volts is the breakdown of the protection device it would be possible to decrease the oxide thickness to approximately 100 angstroms. This would increase the drive by approximately 40% over the thin gate protected circuit.
The N+ and P+ diffusions available in CMOS processes may be used to make a diode but since these two diffusions are usually of such high concentrations, they lead to poor I/V characteristics, i.e., they are usually very leaky and have very poor V/I knee characteristics. These characteristics make such a diode a poor candidate for a protection device, having a typical breakdown of 4.5 volts, and unacceptably less than the typical 5.0 volt power supply voltage.